Velocity Raptor LX665 Manual de usuario

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(12)
United
States
Patent
US006311264B1
(10)
Patent
N0.:
US
6,311,264
B1
Boutaud
et
al.
(45)
Date
of
Patent:
*Oct.
30,
2001
(54)
DIGITAL
SIGNAL
PROCESSOR
WITH
WAIT
4,074,351
2/1978
Boone
et
al.
......................
..
364/200
STATE
REGISTER
. .
(List
continued
on
next
page.)
(75)
Inventors:
Frederic
Boutaud,
Roquefort
les
Pins
OTHER
PUBLICATIONS
(FR);
Peter N.
Ehlig,
Houston,
TX
(Us)
Second
Generation
TMS320
User’s
Guide
;
p.
3—6,
5—2—5—7,
3—34.*
(73)
Assignee:
Texas
Instruments
Incorporated,
Lin
et
al.
The
TMS320
Family
of
Digital
Signal
Processors
Dallas,
TX
(US)
pp.
1143—1159.*
First—Generation
TMS320
User’s
Guide,
Texas
Instruments,
(
*
)
Notice:
Subject
to
any
disclaimer,
the
term
of
this
pp.
3—9,
A—1—20,
6—2—5,
Apr.
1988.
patent
is
extended
or
adjusted
under
35
“DSP56000
Digital
Signal
Processor’s
User’s
Manual”,
U.S.C.
154(b)
by
0
days.
Motorola,
1986,
pp.
2—12—18,
3—2,
7—1—3.
“DSP96001”,
Motorola,
1988,
pp.
1,
2, 6,
9,
10.
This
patent
is
subject
to
a
terminal
dis-
Second—Generation
TMS320
User’s
Guide,
Texas
Instru
claimer.
ments,
pp.
6—10—26,Dec.
1987.
_
Primary
Examiner—Larry
D.
Donaghue
(21)
Appl'
NO"
09/431’504
(74)
Attorney,
Agent,
or
Firm—LaWrence
J.
Bassuk;
(22)
Filed:
Nov.
1,
1999
Frederick
J-
Telecky
Related
US.
Application
Data
(57)
ABSTRACT
_ _ _ _ _
A
data
processing
device
is
used
With
peripheral
devices
(62)
Dlvlslon
9f
a_PPh°aF19n_
NO-
09/390388:
?led
on
JUL
23:
having
addressees
and
differing
communication
response
1999,
which
is
a
division
of
application
No.
08/906,863,
-
d
Th
d
t
-
d
- -
1
d
d-
-t
1
?led
on Aug.
6,
1997,
now
Pat.
No.
5,946,483,
which
is
a
Pen‘)
5'
e a a
procesmg
,evlce
me
‘1
65
a
lgl?‘
Pro‘
division
of
application
No_
08/293,259’
?led
on
Aug
19’
cessor
adapted
for
selecting
different
ones
of
the
peripheral
1994,
now
Pat.
No.
5,907,714,
and
a
continuation
of
appli-
devices
by
asserting
addresses
of
each
selected
peripheral
Canon
N°-_07/_967:942:_?1ed_
on
Oct-
28:
1992:
now
aban'
device.
Addressable
programmable
registers
hold
Wait
state
doned,
which
is
a
continuation
of
application
No.
07/347,
- - - -
967
?led
on
May
4
1989
now
abandoned
values
representative
of
distinct
numbers
of Wait
states
7
'
corresponding
to
different
address
ranges.
Circuitry
respon
IIlt-
Cl-
....................................................
..
siVe
[0
an
asserted
address
to
the
peripheral
devices
asserted
(52)
US.
Cl.
................
..
712/38; 710/16;
713/401
by
the
digital
processor
generates
the
number
of Wait
states
(58)
Field
of
Search
...................................
..
713/501,
502,
represented
by
the
value
held
in
one
of
the
addressable
713/600,
401;
712/38,
43;
710/130,
16
programmable
registers
corresponding
to
the
one
of
the
address
ranges
in
Which
the
asserted
address
occurs,
thereby
(56)
References
Cited
accommodating
the
differing
communication
response
peri
U'S'
PATENT
DOCUMENTS
ods
of
the
peripheral
devices.
3,757,306
9/1973
Boone
.............................
..
340/1725
8
Claims, 18
Drawing
Sheets
R—DY
\
DATA
ADDRESS
<:V>
9/71
978
SEL
973
A
"
111A
WAIT
STATE
TIT
3
M58
GENERATOR
DECODER
l
4-BIT
COUNTER
T
M
974
977
,9
0/
\—>
PWSRO
;>
PWSRl
PERIPHERAL
\-—->
DWSRO
959/
ADDR
BUS
\
>
Dwsm
g>
lWSRO
V
\——>
lWSRl
;>
lWSRZ
IWSRI’)
i
D‘
1110
'
/
9
7:5
DATA
g
C
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Indice de contenidos

Pagina 1 - <:V>

(12) United States Patent US006311264B1 (10) Patent N0.: US 6,311,264 B1 Boutaud et al. (45) Date of Patent: *Oct. 30, 2001 (54) DIGITAL SIGNAL PROCES

Pagina 2 - 6,311,264

U.S. Patent Oct. 30, 2001 Sheet 8 0f 18 US 6,311,264 B1 6%‘ ROM H ‘ / 619 607.1 G 21 ALU MULT f53 ‘ A VIDEO ' I I ‘ ' DISPLAY - CONVERTER g

Pagina 3 - 1 1 1

U.S. Patent 0111. 30, 2001 Sheet 9 0f 18 US 6,311,264 B1 659 653 655 6/57 \ / DISPLAY 6?] DSP CONTROL GSP _’ INTERFACE HOST _ > ,up ADDRESS Mp f

Pagina 4 - 153 x13

U.S. Patent 0111. 30, 2001 Sheet 10 of 18 US 6,311,264 B1 771 779\ % MODEM #C VOCODER 1 E """""""" "&quo

Pagina 6 - /"

U.S. Patent 0a. 30, 2001 Sheet 12 of 18 US 6,311,264 B1 CPU READ IACK INPUT MAIN . REGISTER A CPU WRITE’? “ ‘ RETE ~ 1/ = Q D l/ 855/ OE COUNTERPART —

Pagina 8

U.S. Patent 0a. 30, 2001 Sheet 14 of 18 US 6,311,264 B1 R—DY > ' \ ’ DATA ADDRESS 9/71 978 SEL 973 A ‘ 1, ‘HA wA|T sTATE TN 3 M88 GENERATOR /

Pagina 9

U.S. Patent 0a. 30, 2001 Sheet 15 of 18 US 6,311,264 B1 PIPELINE CYCLE I 2 3 4 5 6 7 ‘I | FETCH |DEc0DE| READ |ExECLITE| 2 | FETCH |DECODE| READ IEXE

Pagina 10 - CONTROL

U.S. Patent 061. 30, 2001 Sheet 16 0f 18 US 6,311,264 B1 Bcnd INSTRUCTION ACC=O AGG<0 OVERFLOW CARRY MANY SHORT ‘NSTRUCHONS STATUS 1 | | | l 1

Pagina 12 - T————co1/1PARE—>Tc

US 6,311,264 B1 Page 2 US. PATENT DOCUMENTS 4,713,748 12/1987 Magar et a1. ... .. 364/200 4,772,888 9/1988 Kimura ...

Pagina 13

U.S. Patent 0a. 30, 2001 Sheet 18 of 18 US 6,311,264 B1 IO5I TART 63 Q \ I: A :> LOAD CKT.BDS. 1077 SUPPLY I / LOAD KEYLESS REORIENT 21> DEVICES

Pagina 23

U.S. Patent 0111. 30, 2001 Sheet 1 of 18 US 6,311,264 B1 F I G. 7a W11 PROG ADDRESS / / PROG DATA 1 1 1 1 1 WT BMAR MUX 95 1 ‘ / ‘ 231\ INT 160 CONTR

Pagina 34

U.S. Patent 0111. 30, 2001 Sheet 2 of 18 US 6,311,264 B1 FROM [10. 10 ,N N‘ = DBMR f223 101D\. _/111D ‘ 241 / BlM R = k ‘ V DATA / 153 x13 1 1 1 ‘

Pagina 45

U.S. Patent 0111. 30, 2001 Sheet 3 of 18 US 6,311,264 B1 305 \. 301 A ' O f 11 DSP ~5- : MOTOR 3 5-’ CPU T - INDUSTRIAL I_1 F ' 500 PROCESS

Pagina 48

U.S. Patent 0a. 30, 2001 Sheet 4 0f 18 US 6,311,264 B1 401 403 405 406 \ / / / REFERENCE r(IT) DIGITAL u(n)_ ZOH HIT)~ (DC SERVO) y(il)_ DISK‘ INPUT

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